A self-timed or self-resetting memory array is a memory array that uses dynamic pulse circuit techniques, which assumes pulsed signals applied to the inputs. In logic circuits, such as those used to select addresses within the memory device, data (logical 0s and 1s) are represented by dynamic pulses on a node, rather than static voltage levels. Although there are performance advantages, pulsed logic and self-timed arrays also pose some problems regarding testability. Prior art self-timed memory arrays are often difficult to debug due to race conditions, and difficult to adequately stress during burn-in.
Race conditions may occur when two pulses that are intended to AND do not arrive with sufficient overlap to ensure the proper evaluation. Also, race conditions may occur when one signal in the AND is supposed to be off before the second signal arrives. If the second signal arrives early, while the first signal is turning off, the circuit may evaluate incorrectly, causing the wrong logic state to be propagated.
An example of this type of race condition in the prior art is shown in FIGS. 1 and 2. In FIG. 1, Input A 10 and Input B 12 are both active high. Both inputs must remain high for a sufficient overlap of time to cause INT 14 to go low, and thus the word line 16 to go high. A timing diagram is shown in FIG. 2. As shown, if Input A 10 and Input B 12 go high and overlap for a sufficient period of time, INT 14 will go low, and the word line 16 will go high. However, when an unacceptable A-B skew occurs and Input A 10 and Input B 12 do not overlap, INT 14 will remain high, and word line 16 will not go high.
Race conditions for addresses or data can occur due to a variety of problems:
1. Voltage variations across the chip.
2. Temperature variation due to local power heating.
3. Variations in poly-silicon line width can cause variations in the effective current of the CMOS transistors.
4. Variations in wiring, wiring resistance, or coupling.
5. The particular design chosen by the design engineer.
An example of a particular design in which a race condition is a typical design constraint is illustrated in the prior art NOR-NAND decoder depicted in FIG. 3, along with its associated timing diagram in FIG. 4. As shown in FIG. 3, NOR circuit 30 is the input to WNOR 32. There is one NOR circuit 30 and one AND circuit 34 for each word line in the memory array. NFET 36 can be shared across many word line decoders. To accomplish this, one nFET 36 would be connected to half of the AND circuits 34, and a second nFET would be connected to the other half of the AND circuits 34.
The function of NOR circuit 30 is to deselect all but one WNOR 32. All WNOR 32 lines are precharged high and then all but one are deselected, or pulled low, before ADD4 38 goes high. Both WNOR 32 and ADD4 38 must be active high for a sufficient overlap in time in order for INT 40, and thus the correct word line 44, to be selected.
The timing diagram in FIG. 4 illustrates the timing of the NOR-NAND decoder. For illustration purposes only, we assume two WNOR 32 lines and two word lines 44. As shown in FIG. 4, all WNOR 32 lines are precharged high. All WNOR 32 lines, with the exception of the selected WNOR 32, are deselected, i.e. the deselected WNOR 32 lines go low. ADD4 38 must come in high after the deselected WNOR 32 lines go low, and ADD4 38 and the selected WNOR 32 must overlap for a sufficient period of time in order for INT 40 to be discharged, causing the correct word line 42 to become active. It is important that all other WNORs 32 are deselected before ADD4 38 goes high. If two WNORs 32 are high (selected) at the same time, then when ADD4 38 goes high, causing node x 42 to go low, two word lines 44 will be selected at the same time.
Race conditions in hardware are difficult to debug and test. Furthermore, it is often difficult to distinguish between logic or software errors and timing errors.
Another problem with prior art self-timed memory arrays is that the decoders are not adequately stressed during burn-in. This is because the restore time of the decoders is usually independent of the cycle time. Yet another problem with prior art self-timed memory arrays is that the arrays are often not functional at burn-in. The solution in the prior art is to add extra noise margin to the array circuitry, such as the decoders. This allows the arrays to be functional at burn-in. However, this approach adds additional delay time to the entire circuit, which is not desirable after the array has been burned in and is operating in functional mode.
Consequently, it would be desirable to have a self-timed memory array that could function properly at a slower cycle time, even when race conditions cause the array to be non-functional at the expected clock frequency. It would also be desirable to have controlled address selection to prevent multiple word lines from being selected, and to have the address lines reset correctly. In addition, it would be desirable to have controlled writing of data to memory locations, so that while the data to be written is settling out, it is not inadvertently written, and so that data (whether correct or erroneous) is not written to a wrong location in the array while the logic is stabilizing. Finally, it would be desirable to have a self-timed array where the decoding could be slowed to allow for more stress coverage during burn-in and where the array would be functional at burn-in without the addition of extra noise margin.